Messages in this thread | | | From | Martin Blumenstingl <> | Subject | [PATCH 0/1] clk: meson: fix PLL rate rounding | Date | Sun, 24 Mar 2019 17:43:26 +0100 |
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Hi Jerome,
can you please look at this small fix? I discovered that my Odroid-C1 wasn't booting anymore. My other Meson8m2 board was using fine.
While investigating this I found that it hangs while setting the sys_pll_dco rate. This is important because unlike Odroid-C1 my Meson8m2 board has a fixed regulator (and thus always runs at a fixed CPU speed). It always hanged while trying to set a CPU frequency of 312MHz. This can be achieved with: 24MHz (xtal) * 52 (m) / 1 (n) / 4 (sys_pll) However, my added debug logging showed that it was trying to set an M value of 51, resulting in an output frequency of 306MHz. My debug logs showed that meson_clk_get_pll_settings() considers 1248MHz (which is the rate requested for sys_pll_dco for a CPU frequency of 312MHz) "worse" than 1224MHz.
I'm not sure exactly why the bug caused the board to hang, but my patch fixes it.
Please apply this to v5.1-rc as I believe the Odroid-C1 on kernelci also suffers from this issue.
Martin Blumenstingl (1): clk: meson: pll: fix rounding and setting a rate that matches precisely
drivers/clk/meson/clk-pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
-- 2.21.0
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