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    Subject[PATCH V2 06/23] perf/x86: Support constraint ranges
    Date
    From: Andi Kleen <ak@linux.intel.com>

    Icelake extended the general counters to 8, even when SMT is enabled.
    However only a (large) subset of the events can be used on all 8
    counters.

    The events that can or cannot be used on all counters are organized
    in ranges.

    We need a lot of scheduler constraints to handle all this.

    To avoid blowing up the tables add event code ranges to the constraint
    tables, and a new inline function to match them.

    Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Signed-off-by: Andi Kleen <ak@linux.intel.com>
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    ---

    Changes since V1:
    - Use 'size' to replace 'range_end'

    arch/x86/events/intel/core.c | 2 +-
    arch/x86/events/intel/ds.c | 2 +-
    arch/x86/events/perf_event.h | 38 ++++++++++++++++++++++++++++++------
    3 files changed, 34 insertions(+), 8 deletions(-)

    diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
    index 620beae035a0..d5d796e114a1 100644
    --- a/arch/x86/events/intel/core.c
    +++ b/arch/x86/events/intel/core.c
    @@ -2688,7 +2688,7 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,

    if (x86_pmu.event_constraints) {
    for_each_event_constraint(c, x86_pmu.event_constraints) {
    - if ((event->hw.config & c->cmask) == c->code) {
    + if (constraint_match(c, event->hw.config)) {
    event->hw.flags |= c->flags;
    return c;
    }
    diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
    index c50de696fb44..04900f393f4e 100644
    --- a/arch/x86/events/intel/ds.c
    +++ b/arch/x86/events/intel/ds.c
    @@ -858,7 +858,7 @@ struct event_constraint *intel_pebs_constraints(struct perf_event *event)

    if (x86_pmu.pebs_constraints) {
    for_each_event_constraint(c, x86_pmu.pebs_constraints) {
    - if ((event->hw.config & c->cmask) == c->code) {
    + if (constraint_match(c, event->hw.config)) {
    event->hw.flags |= c->flags;
    return c;
    }
    diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
    index 132130f00c36..c1762b50fc4c 100644
    --- a/arch/x86/events/perf_event.h
    +++ b/arch/x86/events/perf_event.h
    @@ -49,11 +49,12 @@ struct event_constraint {
    unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
    u64 idxmsk64;
    };
    - u64 code;
    - u64 cmask;
    - int weight;
    - int overlap;
    - int flags;
    + u64 code;
    + u64 cmask;
    + int weight;
    + int overlap;
    + int flags;
    + unsigned int size;
    };
    /*
    * struct hw_perf_event.flags flags
    @@ -71,6 +72,10 @@ struct event_constraint {
    #define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
    #define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */

    +static inline bool constraint_match(struct event_constraint *c, u64 ecode)
    +{
    + return ((ecode & c->cmask) - c->code) <= (u64)c->size;
    +}

    struct amd_nb {
    int nb_id; /* NorthBridge id */
    @@ -263,18 +268,25 @@ struct cpu_hw_events {
    void *kfree_on_online[X86_PERF_KFREE_MAX];
    };

    -#define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
    +#define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
    { .idxmsk64 = (n) }, \
    .code = (c), \
    + .size = (e) - (c), \
    .cmask = (m), \
    .weight = (w), \
    .overlap = (o), \
    .flags = f, \
    }

    +#define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
    + __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
    +
    #define EVENT_CONSTRAINT(c, n, m) \
    __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)

    +#define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
    + __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
    +
    #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
    __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
    0, PERF_X86_EVENT_EXCL)
    @@ -309,6 +321,12 @@ struct cpu_hw_events {
    #define INTEL_EVENT_CONSTRAINT(c, n) \
    EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)

    +/*
    + * Constraint on a range of Event codes
    + */
    +#define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
    + EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
    +
    /*
    * Constraint on the Event code + UMask + fixed-mask
    *
    @@ -356,6 +374,9 @@ struct cpu_hw_events {
    #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
    EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)

    +#define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
    + EVENT_CONSTRAINT_RANGE(c, e, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
    +
    /* Check only flags, but allow all event/umask */
    #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
    EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
    @@ -372,6 +393,11 @@ struct cpu_hw_events {
    ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
    HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)

    +#define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
    + __EVENT_CONSTRAINT_RANGE(code, end, n, \
    + ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
    + HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
    +
    #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
    __EVENT_CONSTRAINT(code, n, \
    ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
    --
    2.17.1
    \
     
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