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SubjectRe: [PATCH v2 1/8] drm/bridge: dw-hdmi: Add SCDC and TMDS Scrambling support
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Hi Rob,

On 14/03/2019 21:14, Rob Herring wrote:
> On Thu, Mar 14, 2019 at 3:07 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>

[...]

>
> Here's with edid-decode:
>
> EDID version: 1.3
> Manufacturer: CYX Model 101 Serial Number 16843009
> Made in week 28 of 2018
> Digital display
> Maximum image size: 22 cm x 13 cm
> Gamma: 2.20
> DPMS levels: Off
> Undefined display color type
> Default (sRGB) color space is primary color space
> First detailed timing is preferred timing
> Display x,y Chromaticity:
> Red: 0.6455, 0.3300
> Green: 0.3095, 0.6171
> Blue: 0.1523, 0.0732
> White: 0.3134, 0.3291
> Established timings supported:
> 640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz
> 800x600@60Hz 4:3 HorFreq: 37900 Hz Clock: 40.000 MHz
> 1024x768@60Hz 4:3 HorFreq: 48400 Hz Clock: 65.000 MHz
> Standard timings supported:
> 1920x1080@60Hz 16:9
> 1920x1080@60Hz 16:9
> 1920x1080@60Hz 16:9
> 1440x900@60Hz 16:10 HorFreq: 55500 Hz Clock: 88.750 MHz
> 1400x1050@60Hz 4:3 HorFreq: 64700 Hz Clock: 101.000 MHz
> 1280x1024@60Hz 5:4 HorFreq: 64000 Hz Clock: 108.000 MHz
> 1280x960@60Hz 4:3 HorFreq: 60000 Hz Clock: 108.000 MHz
> 1280x720@60Hz 16:9
> Detailed mode: Clock 267.810 MHz, 220 mm x 130 mm
> 2560 2608 2640 2720 hborder 0
> 1600 1603 1608 1641 vborder 0
> +hsync +vsync
> VertFreq: 59 Hz, HorFreq: 98459 Hz
> Monitor name: CYS-R101
> Serial number:
> Monitor ranges (bare limits): 48-75Hz V, 30-102kHz H, max dotclock 190MHz
> Has 1 extension blocks
> Checksum: 0x8b (valid)
>
> CTA extension block
> Extension version: 3
> 58 bytes of CTA data
> Video data block
> VIC 16 1920x1080@60Hz 16:9 HorFreq: 67500 Hz Clock: 148.500 MHz
> VIC 5 1920x1080i@60Hz 16:9 HorFreq: 33750 Hz Clock: 74.250 MHz
> VIC 4 1280x720@60Hz 16:9 HorFreq: 45000 Hz Clock: 74.250 MHz
> VIC 31 1920x1080@50Hz 16:9 HorFreq: 56250 Hz Clock: 148.500 MHz
> Audio data block
> Linear PCM, max channels 2
> Supported sample rates (kHz): 48 44.1 32
> Supported sample sizes (bits): 24 20 16
> Speaker allocation data block
> Speaker map:
> FL/FR - Front Left/Right
> Vendor-specific data block, OUI 000c03 (HDMI)
> Source physical address 1.0.0.0
> DC_36bit
> DC_30bit
> DC_Y444
> Maximum TMDS clock: 340MHz
> Vendor-specific data block, OUI c45dd8 (HDMI Forum)
> Version: 1
> Maximum TMDS Character Rate: 340MHz
> SCDC Present
> Supports 10-bits/component Deep Color 4:2:0 Pixel Encoding
> Vendor-specific data block, OUI 00001a
> Extended tag: YCbCr 4:2:0 capability map data block
> VSD Index 17
> VSD Index 18
> Extended tag: Colorimetry data block
> BT2020YCC
> BT2020RGB
> Extended tag: Video capability data block
> YCbCr quantization: Selectable (via AVI YQ) (1)
> RGB quantization: Selectable (via AVI Q) (1)
> PT scan behaviour: Support both over- and underscan (3)
> IT scan behaviour: Support both over- and underscan (3)
> CE scan behaviour: Support both over- and underscan (3)
> Extended tag: HDR static metadata data block
> Electro optical transfer functions:
> Traditional gamma - SDR luminance range
> SMPTE ST2084
> Supported static metadata descriptors:
> Static metadata type 1
> Desired content max luminance: 89 (343.724 cd/m^2)
> Desired content max frame-average luminance: 89 (343.724 cd/m^2)
> Desired content min luminance: 73 (0.282 cd/m^2)
> Underscans PC formats by default
> Basic audio support
> Supports YCbCr 4:4:4
> Supports YCbCr 4:2:2
> 1 native detailed modes
> Detailed mode: Clock 54.000 MHz, 220 mm x 130 mm
> 2560 2608 2640 2720 hborder 0
> 1440 1443 1448 1481 vborder 0
> +hsync +vsync side by side interleaved
> VertFreq: 13 Hz, HorFreq: 19852 Hz
> Checksum: 0x3c (valid)
>


Thanks for the parsed edid.

I think we have multiple issues :
- This EDID is severely broken, SCDC support doesn't make sense because
"Maximum TMDS Character Rate: 340MHz" and "Supports scrambling for <= 340 Mcsc" is not present
Same for 4:2:0, the IDs in the "YCbCr 4:2:0 capability map data block" refers
to invalid modes 17 & 18 in a mode table containing only 4 entries.
- DW-HDMI should not care if SCDC is present, Max TMDS <= 340MHz and low_rates is not present
- In any case, the SoC should not freeze in this situation, so either the
HDMI_FC_SCRAMBLER_CTRL or HDMI_MC_SWRSTZ writes makes the SoC freeze or
the drm_scdc_set_scrambling() containing i2c write fails, anyway this is
the root issue.

This will need 3 steps :
- an entry in the EDID quirk table to disable SCDC and 420 for this monitor
- a fix in dw-hdmi to ignore this SCDC setup
- an investigation to find why and where the SoC did freeze

Rob, could you give the Commercial name of the display for the EDID quirk table ?

Thanks,

Neil


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