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SubjectRe: [PATCH 2/2] Revert "x86/hpet: Reduce HPET counter read contention"
On Thu, Mar 14, 2019 at 04:42:12PM +0800, Zhenzhong Duan wrote:
> This reverts commit f99fd22e4d4bc84880a8a3117311bbf0e3a6a9dc.
> It's unnecessory after commit "acpi_pm: Fix bootup softlockup due to PMTMR
> counter read contention", the simple HPET access code could be restored.
> On a general system with good TSC, TSC is the final default clocksource.
> So the potential performce loss is only at bootup stage before TSC
> replacing HPET, we didn't observe obvious delay of bootup.

The timeline here is:

- Len took out SKX from native_calibrate_tsc
b51120309348 ("x86/tsc: Fix erroneous TSC rate on Skylake Xeon")

This causes the TSC to run through the calibration code, which
completes _after_ SMP bringup.

- This then caused HPET to be used during SMP bringup, which resulted
in Waiman doing the patch you now propose removing.

Because large (multi-socket) SKX machines would barely boot.

f99fd22e4d4b ("x86/hpet: Reduce HPET counter read contention")

- Now, I figured that was all crazy to begin with, and introduced
clocksource_tsc_early, such that we can run at the guestimate TSC
frequency until we've completed calibration and then swap to the real
TSC clocksource.

aa83c45762a2 ("x86/tsc: Introduce early tsc clocksource")
(and assorted fixes)

This means that we now only use HPET for a very short time in early
boot, _IFF_ TSC is stable.

Now, given the amount of wreckage we still see with TSC, I'm very
reluctant to revert this patch. Because the moment TSC goes out the
window, we're back on HPET, and this patch does make a huge difference.

Yes, its sad, gross and nasty... but the same is true for TSC still being
a trainwreck.


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