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    Subject[PATCH 4.20 019/171] clk: qcom: gcc: Use active only source for CPUSS clocks
    Date
    4.20-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    [ Upstream commit 9ff1a3b4912528f853048ccd9757ba6a2cc75557 ]

    The clocks of the CPUSS such as "gcc_cpuss_ahb_clk_src" is a CRITICAL
    clock and needs to vote on the active only source of XO, so as to keep
    the vote as long as CPUSS is active. Similar rbcpr_clk_src is also has
    the same requirement.

    Signed-off-by: Taniya Das <tdas@codeaurora.org>
    Fixes: 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/qcom/gcc-sdm845.c | 14 ++++++++++----
    1 file changed, 10 insertions(+), 4 deletions(-)

    diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
    index f133b7f5652f..26110e74e086 100644
    --- a/drivers/clk/qcom/gcc-sdm845.c
    +++ b/drivers/clk/qcom/gcc-sdm845.c
    @@ -115,8 +115,8 @@ static const char * const gcc_parent_names_6[] = {
    "core_bi_pll_test_se",
    };

    -static const char * const gcc_parent_names_7[] = {
    - "bi_tcxo",
    +static const char * const gcc_parent_names_7_ao[] = {
    + "bi_tcxo_ao",
    "gpll0",
    "gpll0_out_even",
    "core_bi_pll_test_se",
    @@ -128,6 +128,12 @@ static const char * const gcc_parent_names_8[] = {
    "core_bi_pll_test_se",
    };

    +static const char * const gcc_parent_names_8_ao[] = {
    + "bi_tcxo_ao",
    + "gpll0",
    + "core_bi_pll_test_se",
    +};
    +
    static const struct parent_map gcc_parent_map_10[] = {
    { P_BI_TCXO, 0 },
    { P_GPLL0_OUT_MAIN, 1 },
    @@ -210,7 +216,7 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = {
    .freq_tbl = ftbl_gcc_cpuss_ahb_clk_src,
    .clkr.hw.init = &(struct clk_init_data){
    .name = "gcc_cpuss_ahb_clk_src",
    - .parent_names = gcc_parent_names_7,
    + .parent_names = gcc_parent_names_7_ao,
    .num_parents = 4,
    .ops = &clk_rcg2_ops,
    },
    @@ -229,7 +235,7 @@ static struct clk_rcg2 gcc_cpuss_rbcpr_clk_src = {
    .freq_tbl = ftbl_gcc_cpuss_rbcpr_clk_src,
    .clkr.hw.init = &(struct clk_init_data){
    .name = "gcc_cpuss_rbcpr_clk_src",
    - .parent_names = gcc_parent_names_8,
    + .parent_names = gcc_parent_names_8_ao,
    .num_parents = 3,
    .ops = &clk_rcg2_ops,
    },
    --
    2.19.1


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