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Subject[PATCH v6 01/13] spi: atmel-quadspi: cache MR value to avoid a write access
Date
From: Tudor Ambarus <tudor.ambarus@microchip.com>

Set the controller by default in Serial Memory Mode (SMM) at probe.
Cache Mode Register (MR) value to avoid write access when setting
the controller in serial memory mode at exec_op().

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
v6: no change
v5: collect R-b
v4: s/smm/mr, init controller in serial memory mode by default
v3: update smm value when different. rename mr/smm
v2: cache MR value instead of moving the write access at probe

drivers/spi/atmel-quadspi.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index ddc712410812..d6864d29f294 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -155,6 +155,7 @@ struct atmel_qspi {
struct clk *clk;
struct platform_device *pdev;
u32 pending;
+ u32 mr;
struct completion cmd_completion;
};

@@ -238,7 +239,14 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
icr = QSPI_ICR_INST(op->cmd.opcode);
ifr = QSPI_IFR_INSTEN;

- qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
+ /*
+ * If the QSPI controller is set in regular SPI mode, set it in
+ * Serial Memory Mode (SMM).
+ */
+ if (aq->mr != QSPI_MR_SMM) {
+ qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
+ aq->mr = QSPI_MR_SMM;
+ }

mode = find_mode(op);
if (mode < 0)
@@ -381,6 +389,10 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
/* Reset the QSPI controller */
qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);

+ /* Set the QSPI controller by default in Serial Memory Mode */
+ qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
+ aq->mr = QSPI_MR_SMM;
+
/* Enable the QSPI controller */
qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);

--
2.9.5
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