Messages in this thread | | | Date | Mon, 4 Feb 2019 10:45:49 -0800 | From | Fenghua Yu <> | Subject | Re: [PATCH v3 09/10] x86/split_lock: Define #AC for split lock feature |
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On Mon, Feb 04, 2019 at 10:41:40AM -0800, Dave Hansen wrote: > On 2/1/19 9:14 PM, Fenghua Yu wrote: > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -221,6 +221,7 @@ > > #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ > > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ > > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > > +#define X86_FEATURE_AC_SPLIT_LOCK ( 7*32+31) /* #AC for split lock */ > > The last time this was posted, we (Intel) promised to go get the proper > (CPUID or MSR-based) enumeration of this feature documented. Did we do > that? If so, where is that documentation?
As said in the cover patch: "Please note: The feature could be enumerated through MSR IA32_CORE_CAPABILITY (0xCF). But the enumeration is not completely published yet. So this patch set doesn't include the method."
In SDM and ISE, bit 5 in IA32_CORE_CAPABILITY is for enumeration for the split lock feature. But how to enumerate IA32_CORE_CAPABILITY MSR itself is not public yet.
That's why I didn't include the enumeration patches for IA32_CORE_CAPABILITY and the split lock feature. The enumeration patches will be published once the complete enumerations for both IA32_CORE_CAPABILITY and the split lock feature is publicly released.
This patch set only uses "setcpuid=ac_split_lock" to enable the feature.
Thanks.
-Fenghua
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