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    Subject[PATCH v4 4/5] arm64: dts: imx8mq-evk: Enable SAI2 node
    Date
    This sets up clock hierarchy and pin configuration.

    Use PLL1 to derive a proper rate for playing files
    with a rate multiple of 8000.

    Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
    ---
    arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 19 +++++++++++++++++++
    1 file changed, 19 insertions(+)

    diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
    index 54737bf1772f..58de4a3d6029 100644
    --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
    +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
    @@ -52,6 +52,15 @@
    };
    };

    +&sai2 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&pinctrl_sai2>;
    + assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
    + assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
    + assigned-clock-rates = <24576000>;
    + status = "okay";
    +};
    +
    &i2c1 {
    clock-frequency = <100000>;
    pinctrl-names = "default";
    @@ -223,6 +232,16 @@
    >;
    };

    + pinctrl_sai2: sai2grp {
    + fsl,pins = <
    + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
    + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
    + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
    + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
    + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
    + >;
    + };
    +
    pinctrl_i2c1: i2c1grp {
    fsl,pins = <
    MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
    --
    2.17.1
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