Messages in this thread Patch in this message | | | From | Xiaowei Bao <> | Subject | [PATCHv7 1/4] dt-bindings: add DT binding for the layerscape PCIe controller with EP mode | Date | Thu, 21 Feb 2019 11:16:17 +0800 |
| |
Add the documentation for the Device Tree binding for the layerscape PCIe controller with EP mode.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com> Reviewed-by: Minghuan Lian <minghuan.lian@nxp.com> Reviewed-by: Zhiqiang Hou <zhiqiang.hou@nxp.com> Reviewed-by: Rob Herring <robh+dt@kernel.org> --- v2: - Add the SoC specific compatibles. v3: - modify the commit message. v4: - no change. v5: - no change. v6: - no change. v7: - no change.
.../devicetree/bindings/pci/layerscape-pci.txt | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 9b2b8d6..e20ceaa 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -13,6 +13,7 @@ information. Required properties: - compatible: should contain the platform identifier such as: + RC mode: "fsl,ls1021a-pcie" "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" "fsl,ls2088a-pcie" @@ -20,6 +21,8 @@ Required properties: "fsl,ls1046a-pcie" "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" + EP mode: + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- 1.7.1
| |