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SubjectRe: [PATCH v3 5/5] arm64: dts: imx8mq-evk: Enable PCIE0 interface
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Am Dienstag, den 19.02.2019, 17:58 -0800 schrieb Andrey Smirnov:
> Enable PCIE0 interface connected to BCM4356 WiFi/Bluetooth module.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Lucas Stach <l.stach@pengutronix.de>
> Cc: Leonard Crestez <leonard.crestez@nxp.com>
> Cc: "A.s. Dong" <aisheng.dong@nxp.com>
> Cc: Richard Zhu <hongxing.zhu@nxp.com>
> Cc: linux-imx@nxp.com
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org

Reviewed-by: Lucas Stach <l.stach@pengutronix.de>

> ---
> arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 42 ++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> index 64acccc4bfcb..226aeb9791a5 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
> @@ -31,6 +31,12 @@
> gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + pcie0_refclk: pcie0-refclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> };
>
> &fec1 {
> @@ -40,6 +46,17 @@
> status = "okay";
> };
>
> +&gpio5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wifi_reset>;
> +
> + wl-reg-on {
> + gpio-hog;
> + gpios = <29 GPIO_ACTIVE_HIGH>;
> + output-high;
> + };
> +};
> +
> &i2c1 {
> clock-frequency = <100000>;
> pinctrl-names = "default";
> @@ -131,6 +148,18 @@
> };
> };
>
> +&pcie0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie0>;
> + reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
> + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> + <&clk IMX8MQ_CLK_PCIE1_AUX>,
> + <&clk IMX8MQ_CLK_PCIE1_PHY>,
> + <&pcie0_refclk>;
> + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> + status = "okay";
> +};
> +
> &uart1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_uart1>;
> @@ -195,6 +224,13 @@
> >;
> };
>
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
> + MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
> + >;
> + };
> +
> pinctrl_reg_usdhc2: regusdhc2grpgpio {
> fsl,pins = <
> MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> @@ -300,4 +336,10 @@
> MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> >;
> };
> +
> + pinctrl_wifi_reset: wifiresetgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
> + >;
> + };
> };

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