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SubjectRe: [PATCH 2/4] pwm: atmel: add support for controllers with 32 bit counters
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On 19.02.2019 09:42, Uwe Kleine-König wrote:
> Hello Claudiu,
>
> On Mon, Jan 21, 2019 at 12:30:53PM +0000, Claudiu.Beznea@microchip.com wrote:
>> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>>
>> New SAM9X60's PWM controller use 32 bits counters thus it could generate
>> signals with higher period and duty cycles. Update the current driver
>> to work with old controller (that uses 16 bits counters) and with the
>> new SAM9X60's controller.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
>> ---
>> drivers/pwm/pwm-atmel.c | 38 +++++++++++++++++++++++++++-----------
>> 1 file changed, 27 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
>> index 7e86a5266eb6..44f4a1c9f60b 100644
>> --- a/drivers/pwm/pwm-atmel.c
>> +++ b/drivers/pwm/pwm-atmel.c
>> @@ -48,15 +48,15 @@
>> #define PWMV2_CPRD 0x0C
>> #define PWMV2_CPRDUPD 0x10
>>
>> -/*
>> - * Max value for duty and period
>> - *
>> - * Although the duty and period register is 32 bit,
>> - * however only the LSB 16 bits are significant.
>> - */
>> -#define PWM_MAX_DTY 0xFFFF
>> -#define PWM_MAX_PRD 0xFFFF
>> -#define PRD_MAX_PRES 10
>> +/* Max values for period and prescaler */
>> +
>> +/* Only the LSB 16 bits are significant. */
>> +#define PWM_MAXV1_PRD 0xFFFF
>> +
>> +/* All 32 bits are significant. */
>> +#define PWM_MAXV2_PRD 0xFFFFFFFF
>
> This symbol is unused, so I wonder if the patch really does what the
> commit log promises.

It is only of SAM9X60's PWM. Please check patch 3/4. Maybe I should have
been introduced it in there. If you consider it is better to be introduced
in patch 3/4 please let me know.

>
> Best regards
> Uwe
>
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