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SubjectRe: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
Hi,

* Lokesh Vutla <lokeshvutla@ti.com> [190212 07:43]:
> +The Interrupt Router (INTR) module provides a mechanism to route M
> +interrupt inputs to N interrupt outputs, where all M inputs are selectable
> +to be driven per N output. There is one register per output (MUXCNTL_N) that
> +controls the selection.
> +
> +
> + Interrupt Router
> + +----------------------+
> + | Inputs Outputs |
> + +-------+ | +------+ |
> + | GPIO |----------->| | irq0 | | Host IRQ
> + +-------+ | +------+ | controller
> + | . +-----+ | +-------+
> + +-------+ | . | 0 | |----->| IRQ |
> + | INTA |----------->| . +-----+ | +-------+
> + +-------+ | . . |
> + | +------+ . |
> + | | irqM | +-----+ |
> + | +------+ | N | |
> + | +-----+ |
> + +----------------------+

Is this always one-to-one mapping or can the same interrupt be routed to
multiple targets like to the SoC and some coprocessor?

> +Configuration of these MUXCNTL_N registers is done by a system controller
> +(like the Device Memory and Security Controller on K3 AM654 SoC). System
> +controller will keep track of the used and unused registers within the Router.
> +Driver should request the system controller to get the range of GIC IRQs
> +assigned to the requesting hosts. It is the drivers responsibility to keep
> +track of Host IRQs.
> +
> +Communication between the host processor running an OS and the system
> +controller happens through a protocol called TI System Control Interface
> +(TISCI protocol). For more details refer:
> +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt

Care to describe a bit why the interrupts need to be routed by a system
controller?

Regards,

Tony

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