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    Subject[PATCH 4.20 116/352] clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
    Date
    4.20-stable review patch.  If anyone has any objections, please let me know.

    ------------------

    [ Upstream commit 6e6da2039c82271dd873b9ad2b902a692a7dd554 ]

    All the audio interfaces on Allwinner SoCs need to change their module
    clocks during operation, to switch between support for 44.1 kHz and 48
    kHz family sample rates. The clock rate for the module clocks is
    governed by their upstream audio PLL. The module clocks themselves only
    have a gate, and sometimes a divider or mux. Thus any rate changes need
    to be propagated upstream.

    Set the CLK_SET_RATE_PARENT flag for all audio module clocks to achieve
    this.

    Signed-off-by: Chen-Yu Tsai <wens@csie.org>
    Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 6 +++---
    1 file changed, 3 insertions(+), 3 deletions(-)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
    index 13eb5b23c5e7..c40d572a7602 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c
    @@ -366,10 +366,10 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
    static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
    "pll-audio-2x", "pll-audio" };
    static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
    - 0x0b0, 16, 2, BIT(31), 0);
    + 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);

    static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
    - 0x0b4, 16, 2, BIT(31), 0);
    + 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);

    /* TODO: the parent for most of the USB clocks is not known */
    static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
    @@ -446,7 +446,7 @@ static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
    static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
    0x140, BIT(31), CLK_SET_RATE_PARENT);
    static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
    - 0x140, BIT(30), 0);
    + 0x140, BIT(30), CLK_SET_RATE_PARENT);
    static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
    0x144, BIT(31), 0);

    --
    2.19.1


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