Messages in this thread | | | Subject | Re: [RFC 1/3] KVM: arm64: pmu: Don't increment SW INCR if PMCR.E is unset | Date | Thu, 05 Dec 2019 09:54:11 +0000 | From | Marc Zyngier <> |
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On 2019-12-04 20:44, Eric Auger wrote: > The specification says PMSWINC increments PMEVCNTR<n>_EL1 by 1 > if PMEVCNTR<n>_EL0 is enabled and configured to count SW_INCR. > > For PMEVCNTR<n>_EL0 to be enabled, we need both PMCNTENSET to > be set for the corresponding event counter but we also need > the PMCR.E bit to be set. > > Fixes: 7a0adc7064b8 ("arm64: KVM: Add access handler for PMSWINC > register") > Signed-off-by: Eric Auger <eric.auger@redhat.com> > --- > virt/kvm/arm/pmu.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c > index 8731dfeced8b..c3f8b059881e 100644 > --- a/virt/kvm/arm/pmu.c > +++ b/virt/kvm/arm/pmu.c > @@ -486,6 +486,9 @@ void kvm_pmu_software_increment(struct kvm_vcpu > *vcpu, u64 val) > if (val == 0) > return; > > + if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E)) > + return; > + > enable = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0); > for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) { > if (!(val & BIT(i)))
Acked-by: Marc Zyngier <maz@kernel.org>
M. -- Jazz is not dead. It just smells funny...
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