Messages in this thread | | | Subject | Re: [PATCH v2] mtd: spi-nor: Fix the writing of the Status Register on micron flashes | From | John Garry <> | Date | Wed, 4 Dec 2019 10:18:37 +0000 |
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On 03/12/2019 14:50, Tudor.Ambarus@microchip.com wrote: > From: Tudor Ambarus <tudor.ambarus@microchip.com> > > Micron flashes do not support 16 bit writes on the Status Register. > According to micron datasheets, when using the Write Status Register > (01h) command, the chip select should be driven LOW and held LOW until > the eighth bit of the last data byte has been latched in, after which > it must be driven HIGH. If CS is not driven HIGH, the command is not > executed, flag status register error bits are not set, and the write enable > latch remains set to 1. This fixes the lock operations on micron flashes. > > Reported-by: John Garry <john.garry@huawei.com> > Fixes: 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()") > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Thanks,
Tested-by: John Garry <john.garry@huawei.com>
> --- > v2: reword commit subject > > drivers/mtd/spi-nor/spi-nor.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c > index f1490c7b5cb9..7e41493f69d8 100644 > --- a/drivers/mtd/spi-nor/spi-nor.c > +++ b/drivers/mtd/spi-nor/spi-nor.c > @@ -4607,6 +4607,7 @@ static void sst_set_default_init(struct spi_nor *nor) > static void st_micron_set_default_init(struct spi_nor *nor) > { > nor->flags |= SNOR_F_HAS_LOCK; > + nor->flags &= ~SNOR_F_HAS_16BIT_SR; > nor->params.quad_enable = NULL; > nor->params.set_4byte = st_micron_set_4byte; > } >
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