Messages in this thread Patch in this message | | | Date | Mon, 30 Dec 2019 17:24:48 +0530 | From | afzal mohammed <> | Subject | [RFC PATCH 1/2] ARM: !MMU: v7-M: prepare preemption support |
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Rearrange getting thread_info pointer & popping lr so as to have an easy to review diff for preempt support that is going to be added.
Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com> --- arch/arm/kernel/entry-v7m.S | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/kernel/entry-v7m.S b/arch/arm/kernel/entry-v7m.S index de1f20624be1..581562dbecf3 100644 --- a/arch/arm/kernel/entry-v7m.S +++ b/arch/arm/kernel/entry-v7m.S @@ -48,7 +48,7 @@ strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n" @ routine called with r0 = irq number, r1 = struct pt_regs * bl nvic_handle_irq - pop {lr} + get_thread_info tsk @ @ Check for any pending work if returning to user @ @@ -57,7 +57,6 @@ strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n" tst r0, V7M_SCB_ICSR_RETTOBASE beq 2f - get_thread_info tsk ldr r2, [tsk, #TI_FLAGS] tst r2, #_TIF_WORK_MASK beq 2f @ no work pending @@ -65,6 +64,8 @@ strerr: .asciz "\nUnhandled exception: IPSR = %08lx LR = %08lx\n" str r0, [r1, V7M_SCB_ICSR] @ raise PendSV 2: + pop {lr} + @ registers r0-r3 and r12 are automatically restored on exception @ return. r4-r7 were not clobbered in v7m_exception_entry so for @ correctness they don't need to be restored. So only r8-r11 must be -- 2.24.1
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