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    Subject[PATCH 4.19 001/321] clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
    Date
    From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>

    [ Upstream commit 44b09b11b813b8550e6b976ea51593bc23bba8d1 ]

    The meson-saradc driver manually sets the input clock for
    sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
    GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
    to sar_adc_clk_sel which will let the common clock framework select the
    best matching parent clock if we want that.

    This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
    drivers, which both also specify CLK_SET_RATE_PARENT.

    Fixes: 33d0fcdfe0e870 ("clk: gxbb: add the SAR ADC clocks and expose them")
    Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
    Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/meson/gxbb.c | 1 +
    1 file changed, 1 insertion(+)

    diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
    index 4d4f6d842c31c..d94b65061b9f1 100644
    --- a/drivers/clk/meson/gxbb.c
    +++ b/drivers/clk/meson/gxbb.c
    @@ -836,6 +836,7 @@ static struct clk_regmap gxbb_sar_adc_clk_div = {
    .ops = &clk_regmap_divider_ops,
    .parent_names = (const char *[]){ "sar_adc_clk_sel" },
    .num_parents = 1,
    + .flags = CLK_SET_RATE_PARENT,
    },
    };

    --
    2.20.1


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