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SubjectRe: [PATCH 2/2] clk: socfpga: agilex: add clock driver for the Agilex platform
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Hi Stephen,

On 9/18/19 12:00 AM, Stephen Boyd wrote:
> Quoting Dinh Nguyen (2019-09-17 18:34:59)
>> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
>> index 0cad76021297..ef2c96c0f1e0 100644
>> --- a/drivers/clk/Makefile
>> +++ b/drivers/clk/Makefile
>> @@ -18,6 +18,7 @@ endif
>>

<snip>

>> +struct clk *agilex_register_pll(const char *name,
>> + const char * const *parent_names,
>> + u8 num_parents, unsigned long flags,
>> + void __iomem *reg, unsigned long offset)
>> +{
>> + struct clk *clk;
>> + struct socfpga_pll *pll_clk;
>> + struct clk_init_data init;
>> +
>> + pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
>> + if (WARN_ON(!pll_clk))
>> + return NULL;
>> +
>> + pll_clk->hw.reg = reg + offset;
>> +
>> + if (streq(name, SOCFPGA_BOOT_CLK))
>> + init.ops = &clk_boot_ops;
>> + else
>> + init.ops = &agilex_clk_pll_ops;
>> +
>> + init.name = name;
>> + init.flags = flags;
>> +
>> + init.num_parents = num_parents;
>> + init.parent_names = parent_names;
>
> Is it possible to use the new way of specifying clk parents here so that
> we don't have to keep using strings to describe the clk topology?
>

Can you point me to what you mean here? Perhaps a driver that is using
this new way of specifying clk parents?

Thanks,
Dinh

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