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    Subject[PATCH V5 RESEND 03/14] perf/x86/intel: Move BTS index to 47
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    The bit 48 in the PERF_GLOBAL_STATUS is used to indicate the overflow
    status of PERF_METRICS counters now.

    Move BTS index to 47.

    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    ---

    No changes since V4

    arch/x86/include/asm/perf_event.h | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
    index 55a4d05ba6ec..7df1d5b78aa8 100644
    --- a/arch/x86/include/asm/perf_event.h
    +++ b/arch/x86/include/asm/perf_event.h
    @@ -185,11 +185,11 @@ struct x86_pmu_capability {
    /*
    * We model BTS tracing as another fixed-mode PMC.
    *
    - * We choose a value in the middle of the fixed event range, since lower
    + * We choose value 47 for the fixed index of BTS, since lower
    * values are used by actual fixed events and higher values are used
    * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
    */
    -#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 16)
    +#define INTEL_PMC_IDX_FIXED_BTS (INTEL_PMC_IDX_FIXED + 15)

    #define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
    #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
    --
    2.17.1
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