Messages in this thread | | | Subject | Re: [PATCH v4 0/7] Use 1st-level for IOVA translation | From | Lu Baolu <> | Date | Sun, 22 Dec 2019 15:00:38 +0800 |
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Hi Yi,
On 12/21/19 11:14 AM, Lu Baolu wrote: > Hi again, > > On 2019/12/20 19:50, Liu, Yi L wrote: >> 3) Per VT-d spec, FLPT has canonical requirement to the input >> addresses. So I'd suggest to add some enhance regards to it. >> Please refer to chapter 3.6:-). >> >> 3.6 First-Level Translation >> First-level translation restricts the input-address to a canonical >> address (i.e., address bits 63:N have >> the same value as address bit [N-1], where N is 48-bits with 4-level >> paging and 57-bits with 5-level >> paging). Requests subject to first-level translation by remapping >> hardware are subject to canonical >> address checking as a pre-condition for first-level translation, and a >> violation is treated as a >> translation-fault. > > It seems to be a conflict at bit 63. It should be the same as bit[N-1] > according to the canonical address requirement; but it is also used as > the XD control. Any thought?
Ignore this please. It makes no sense. :-) I confused.
Best regards, baolu
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