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    Subject[PATCH 4.19 22/47] PCI: Apply Cavium ACS quirk to ThunderX2 and ThunderX3
    Date
    From: George Cherian <george.cherian@marvell.com>

    commit f338bb9f0179cb959977b74e8331b312264d720b upstream.

    Enhance the ACS quirk for Cavium Processors. Add the root port vendor IDs
    for ThunderX2 and ThunderX3 series of processors.

    [bhelgaas: add Fixes: and stable tag]
    Fixes: f2ddaf8dfd4a ("PCI: Apply Cavium ThunderX ACS quirk to more Root Ports")
    Link: https://lore.kernel.org/r/20191111024243.GA11408@dc5-eodlnx05.marvell.com
    Signed-off-by: George Cherian <george.cherian@marvell.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: Robert Richter <rrichter@marvell.com>
    Cc: stable@vger.kernel.org # v4.12+
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/pci/quirks.c | 20 +++++++++++++-------
    1 file changed, 13 insertions(+), 7 deletions(-)

    --- a/drivers/pci/quirks.c
    +++ b/drivers/pci/quirks.c
    @@ -4219,15 +4219,21 @@ static int pci_quirk_amd_sb_acs(struct p

    static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
    {
    + if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
    + return false;
    +
    + switch (dev->device) {
    /*
    - * Effectively selects all downstream ports for whole ThunderX 1
    - * family by 0xf800 mask (which represents 8 SoCs), while the lower
    - * bits of device ID are used to indicate which subdevice is used
    - * within the SoC.
    + * Effectively selects all downstream ports for whole ThunderX1
    + * (which represents 8 SoCs).
    */
    - return (pci_is_pcie(dev) &&
    - (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
    - ((dev->device & 0xf800) == 0xa000));
    + case 0xa000 ... 0xa7ff: /* ThunderX1 */
    + case 0xaf84: /* ThunderX2 */
    + case 0xb884: /* ThunderX3 */
    + return true;
    + default:
    + return false;
    + }
    }

    static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)

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