lkml.org 
[lkml]   [2019]   [Dec]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 4.19 037/243] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
    Date
    From: Jagan Teki <jagan@amarulasolutions.com>

    [ Upstream commit ee678706e46d0d185c27cc214ad97828e0643159 ]

    DSI DPHY gate bit on MIPI DSI clock register is bit 15
    not bit 30.

    Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
    Acked-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    index 2a60981799216..dec4a130390a3 100644
    --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
    @@ -582,7 +582,7 @@ static const char * const dsi_dphy_parents[] = { "pll-video0", "pll-periph0" };
    static const u8 dsi_dphy_table[] = { 0, 2, };
    static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
    dsi_dphy_parents, dsi_dphy_table,
    - 0x168, 0, 4, 8, 2, BIT(31), CLK_SET_RATE_PARENT);
    + 0x168, 0, 4, 8, 2, BIT(15), CLK_SET_RATE_PARENT);

    static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
    0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
    --
    2.20.1


    \
     
     \ /
      Last update: 2019-12-11 16:18    [W:4.072 / U:0.048 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site