Messages in this thread | | | Date | Sat, 9 Nov 2019 16:09:53 +0100 | From | Andrew Lunn <> | Subject | Re: [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs |
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On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote: > On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 > have interrupt lines connected to the shared IRQ2_B LS1021A pin. > > The interrupts are active low, but the GICv2 controller does not support > active-low and falling-edge interrupts, so the only mode it can be > configured in is rising-edge.
Hi Vladimir
So how does this work? The rising edge would occur after the interrupt handler has completed? What triggers the interrupt handler?
Andrew
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