Re: [PATCH v2 2/2] clk: ast2600: Add RMII RCLK gates for all four MACs
Date
Fri, 08 Nov 2019 08:48:53 -0800
Quoting Andrew Jeffery (2019-10-09 19:07:25) > RCLK is a fixed 50MHz clock derived from HPLL/HCLK that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > ---