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SubjectRe: [RESEND PATCH v4] rtc: Fix the AltCentury value on AMD/Hygon platform
On 05/11/2019 16:39:43+0800, Jinke Fan wrote:
> When using following operations:
> date -s "21190910 19:20:00"
> hwclock -w
> to change date from 2019 to 2119 for test, it will fail on Hygon
> Dhyana and AMD Zen CPUs, while the same operations run ok on Intel i7
> platform.
>
> MC146818 driver use function mc146818_set_time() to set register
> RTC_FREQ_SELECT(RTC_REG_A)'s bit4-bit6 field which means divider stage
> reset value on Intel platform to 0x7.
>
> While AMD/Hygon RTC_REG_A(0Ah)'s bit4 is defined as DV0 [Reference]:
> DV0 = 0 selects Bank 0, DV0 = 1 selects Bank 1. Bit5-bit6 is defined
> as reserved.
>
> DV0 is set to 1, it will select Bank 1, which will disable AltCentury
> register(0x32) access. As UEFI pass acpi_gbl_FADT.century 0x32
> (AltCentury), the CMOS write will be failed on code:
> CMOS_WRITE(century, acpi_gbl_FADT.century).
>
> Correct RTC_REG_A bank select bit(DV0) to 0 on AMD/Hygon CPUs, it will
> enable AltCentury(0x32) register writing and finally setup century as
> expected.
>
> Test results on Intel i7, AMD EPYC(17h) and Hygon machine show that it
> works as expected.
> Compiling for sparc64 and alpha architectures are passed.
>
> Reference:
> https://www.amd.com/system/files/TechDocs/51192_Bolton_FCH_RRG.pdf
> section: 3.13 Real Time Clock (RTC)
>
> Reported-by: kbuild test robot <lkp@intel.com>
> Signed-off-by: Jinke Fan <fanjinke@hygon.cn>
> ---
>
> v3->v4:
> - Limited modification to AMD EPYC(17h).
> - Change the macro RTC_DV0 to RTC_DIV_RESET2.
> - Make sure save_freq_select's bit4 is cleared.
>
> v2->v3:
> - Make the changes only relevant to AMD/Hygon.
>
> v1->v2:
> - Fix the compile errors on sparc64/alpha platform.
>
> drivers/rtc/rtc-mc146818-lib.c | 15 ++++++++++++++-
> 1 file changed, 14 insertions(+), 1 deletion(-)
>
Applied, thanks.

--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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