Messages in this thread | | | Subject | Re: [patch 4/9] x86/io: Speedup schedule out of I/O bitmap user | From | Andy Lutomirski <> | Date | Fri, 8 Nov 2019 14:41:37 -0800 |
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On 11/7/19 6:08 AM, Thomas Gleixner wrote: > On Thu, 7 Nov 2019, Thomas Gleixner wrote: >> On Thu, 7 Nov 2019, Peter Zijlstra wrote: >>> On Wed, Nov 06, 2019 at 08:35:03PM +0100, Thomas Gleixner wrote: >>>> There is no requirement to update the TSS I/O bitmap when a thread using it is >>>> scheduled out and the incoming thread does not use it. >>>> >>>> For the permission check based on the TSS I/O bitmap the CPU calculates the memory >>>> location of the I/O bitmap by the address of the TSS and the io_bitmap_base member >>>> of the tss_struct. The easiest way to invalidate the I/O bitmap is to switch the >>>> offset to an address outside of the TSS limit. >>>> >>>> If an I/O instruction is issued from user space the TSS limit causes #GP to be >>>> raised in the same was as valid I/O bitmap with all bits set to 1 would do. >>>> >>>> This removes the extra work when an I/O bitmap using task is scheduled out >>>> and puts the burden on the rare I/O bitmap users when they are scheduled >>>> in. >>> >>> This also nicely aligns with that the context switch time is accounted >>> to the next task. So by doing the expensive part on switch-in gets it >>> all accounted to the task that caused it. >> >> Just that I can't add the storage to tss_struct due to the VMX insanity of >> setting TSS limit hard to 0x67 on vmexit instead of restoring the host >> value. > > Well, I can. The build bugon in vmx.c is just bogus.
SDM vol 3 27.5.2 says the BUILD_BUG_ON is right. Or am I misunderstanding you?
I'm reasonably confident that the TSS limit is indeed 0x67 after VM exit, and I wrote the existing code that tries to optimize this to avoid LTR when not needed.
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