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SubjectRe: [PATCH 2/2] PCI: uniphier: Add checking whether PERST# is deasserted
On Thu, Nov 07, 2019 at 01:58:15PM +0900, Kunihiko Hayashi wrote:
> When PERST# is asserted once, EP configuration will be initialized.

I don't quite understand this - does the EP/RC mode depend on how often
PERST# is toggled?

> If PERST# has been already deasserted, it isn't necessary to assert
> here.

What is the motativation for this patch? Is it to avoid a delay during
boot, or to fix some bug? Isn't it nice to always reset the IP before
use anyway?

>
> This checks whether PERST# is deasserted using PCL_PINMON register,
> and adds omit controlling PERST#.

Should this read 'and omits controlling PERST#'?

>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
> drivers/pci/controller/dwc/pcie-uniphier.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
> index 8fd7bad..1ea4220 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier.c
> @@ -22,6 +22,9 @@
>
> #include "pcie-designware.h"
>
> +#define PCL_PINMON 0x0028
> +#define PCL_PINMON_PERST_OUT BIT(16)
> +
> #define PCL_PINCTRL0 0x002c
> #define PCL_PERST_PLDN_REGEN BIT(12)
> #define PCL_PERST_NOE_REGEN BIT(11)
> @@ -100,6 +103,11 @@ static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
> val |= PCL_SYS_AUX_PWR_DET;
> writel(val, priv->base + PCL_APP_PM0);
>
> + /* return if PERST# is already deasserted */

This comment just describes what the following line does which may be
self-explanatory, perhaps a better comment would describe why we avoid
a reset.

Thanks,

Andrew Murray

> + val = readl(priv->base + PCL_PINMON);
> + if (val & PCL_PINMON_PERST_OUT)
> + return;
> +
> /* assert PERST# */
> val = readl(priv->base + PCL_PINCTRL0);
> val &= ~(PCL_PERST_NOE_REGVAL | PCL_PERST_OUT_REGVAL
> --
> 2.7.4
>

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