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SubjectRe: [PATCH 10/17] firmware: qcom_scm-32: Use SMC arch wrappers
On Mon 04 Nov 17:27 PST 2019, Elliot Berman wrote:

> Use SMC arch wrappers instead of inline assembly.
>

I presume this is the point in the series where you can drop the
CFLAGS_qcom_scm-32.o from the Makefile? Please include that in this
patch.

Regards,
Bjorn

> Signed-off-by: Elliot Berman <eberman@codeaurora.org>
> ---
> drivers/firmware/qcom_scm-32.c | 71 ++++++++++--------------------------------
> 1 file changed, 17 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/firmware/qcom_scm-32.c b/drivers/firmware/qcom_scm-32.c
> index b7f9f28..e3dc9a7 100644
> --- a/drivers/firmware/qcom_scm-32.c
> +++ b/drivers/firmware/qcom_scm-32.c
> @@ -10,6 +10,7 @@
> #include <linux/errno.h>
> #include <linux/err.h>
> #include <linux/qcom_scm.h>
> +#include <linux/arm-smccc.h>
> #include <linux/dma-mapping.h>
>
> #include "qcom_scm.h"
> @@ -121,25 +122,13 @@ static inline void *legacy_get_response_buffer(const struct legacy_response *rsp
> static u32 __qcom_scm_call_do(u32 cmd_addr)
> {
> int context_id;
> - register u32 r0 asm("r0") = 1;
> - register u32 r1 asm("r1") = (u32)&context_id;
> - register u32 r2 asm("r2") = cmd_addr;
> + struct arm_smccc_res res;
> do {
> - asm volatile(
> - __asmeq("%0", "r0")
> - __asmeq("%1", "r0")
> - __asmeq("%2", "r1")
> - __asmeq("%3", "r2")
> -#ifdef REQUIRES_SEC
> - ".arch_extension sec\n"
> -#endif
> - "smc #0 @ switch to secure world\n"
> - : "=r" (r0)
> - : "r" (r0), "r" (r1), "r" (r2)
> - : "r3", "r12");
> - } while (r0 == QCOM_SCM_INTERRUPTED);
> -
> - return r0;
> + arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr,
> + 0, 0, 0, 0, 0, &res);
> + } while (res.a0 == QCOM_SCM_INTERRUPTED);
> +
> + return res.a0;
> }
>
> /**
> @@ -236,24 +225,12 @@ static int qcom_scm_call(struct device *dev, u32 svc_id, u32 cmd_id,
> static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
> {
> int context_id;
> + struct arm_smccc_res res;
> +
> + arm_smccc_smc(LEGACY_ATOMIC(svc, cmd, 1), (unsigned long)&context_id,
> + arg1, 0, 0, 0, 0, 0, &res);
>
> - register u32 r0 asm("r0") = LEGACY_ATOMIC(svc, cmd, 1);
> - register u32 r1 asm("r1") = (u32)&context_id;
> - register u32 r2 asm("r2") = arg1;
> -
> - asm volatile(
> - __asmeq("%0", "r0")
> - __asmeq("%1", "r0")
> - __asmeq("%2", "r1")
> - __asmeq("%3", "r2")
> -#ifdef REQUIRES_SEC
> - ".arch_extension sec\n"
> -#endif
> - "smc #0 @ switch to secure world\n"
> - : "=r" (r0)
> - : "r" (r0), "r" (r1), "r" (r2)
> - : "r3", "r12");
> - return r0;
> + return res.a0;
> }
>
> /**
> @@ -269,26 +246,12 @@ static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
> static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
> {
> int context_id;
> + struct arm_smccc_res res;
> +
> + arm_smccc_smc(LEGACY_ATOMIC(svc, cmd, 2), (unsigned long)&context_id,
> + arg1, arg2, 0, 0, 0, 0, &res);
>
> - register u32 r0 asm("r0") = LEGACY_ATOMIC(svc, cmd, 2);
> - register u32 r1 asm("r1") = (u32)&context_id;
> - register u32 r2 asm("r2") = arg1;
> - register u32 r3 asm("r3") = arg2;
> -
> - asm volatile(
> - __asmeq("%0", "r0")
> - __asmeq("%1", "r0")
> - __asmeq("%2", "r1")
> - __asmeq("%3", "r2")
> - __asmeq("%4", "r3")
> -#ifdef REQUIRES_SEC
> - ".arch_extension sec\n"
> -#endif
> - "smc #0 @ switch to secure world\n"
> - : "=r" (r0)
> - : "r" (r0), "r" (r1), "r" (r2), "r" (r3)
> - : "r12");
> - return r0;
> + return res.a0;
> }
>
> /**
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

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