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    Subject[PATCH v4 06/14] arm64: dts: qcom: sc7180: Add rpmh-rsc node
    Date
    From: Maulik Shah <mkshah@codeaurora.org>

    Add device bindings for the application processor's rsc. The rsc
    contains the TCS that are used for communicating with the hardened
    resource accelerators on Qualcomm Technologies, Inc. (QTI) SoCs.

    Signed-off-by: Maulik Shah <mkshah@codeaurora.org>
    Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
    ---
    arch/arm64/boot/dts/qcom/sc7180.dtsi | 19 +++++++++++++++++++
    1 file changed, 19 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
    index 61250560c7ef..98c8ab7d613c 100644
    --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
    @@ -7,6 +7,7 @@

    #include <dt-bindings/clock/qcom,gcc-sc7180.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    +#include <dt-bindings/soc/qcom,rpmh-rsc.h>

    / {
    interrupt-parent = <&intc>;
    @@ -387,6 +388,24 @@
    status = "disabled";
    };
    };
    +
    + apps_rsc: rsc@18200000 {
    + label = "apps_rsc";
    + compatible = "qcom,rpmh-rsc";
    + reg = <0 0x18200000 0 0x10000>,
    + <0 0x18210000 0 0x10000>,
    + <0 0x18220000 0 0x10000>;
    + reg-names = "drv-0", "drv-1", "drv-2";
    + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
    + qcom,tcs-offset = <0xd00>;
    + qcom,drv-id = <2>;
    + qcom,tcs-config = <ACTIVE_TCS 2>,
    + <SLEEP_TCS 3>,
    + <WAKE_TCS 3>,
    + <CONTROL_TCS 1>;
    + };
    };

    timer {
    --
    QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
    of Code Aurora Forum, hosted by The Linux Foundation
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