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    Subject[PATCH 4.14 170/211] net: phy: dp83867: fix speed 10 in sgmii mode
    Date
    From: Max Uvarov <muvarov@gmail.com>

    commit 333061b924539c0de081339643f45514f5f1c1e6 upstream.

    For supporting 10Mps speed in SGMII mode DP83867_10M_SGMII_RATE_ADAPT bit
    of DP83867_10M_SGMII_CFG register has to be cleared by software.
    That does not affect speeds 100 and 1000 so can be done on init.

    Signed-off-by: Max Uvarov <muvarov@gmail.com>
    Cc: Heiner Kallweit <hkallweit1@gmail.com>
    Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
    Signed-off-by: David S. Miller <davem@davemloft.net>
    [ adapted for kernels without phy_modify_mmd ]
    Signed-off-by: Adrian Bunk <bunk@kernel.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

    ---
    drivers/net/phy/dp83867.c | 19 +++++++++++++++++++
    1 file changed, 19 insertions(+)

    --- a/drivers/net/phy/dp83867.c
    +++ b/drivers/net/phy/dp83867.c
    @@ -37,6 +37,8 @@
    #define DP83867_STRAP_STS1 0x006E
    #define DP83867_RGMIIDCTL 0x0086
    #define DP83867_IO_MUX_CFG 0x0170
    +#define DP83867_10M_SGMII_CFG 0x016F
    +#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)

    #define DP83867_SW_RESET BIT(15)
    #define DP83867_SW_RESTART BIT(14)
    @@ -283,6 +285,23 @@ static int dp83867_config_init(struct ph
    }
    }

    + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
    + /* For support SPEED_10 in SGMII mode
    + * DP83867_10M_SGMII_RATE_ADAPT bit
    + * has to be cleared by software. That
    + * does not affect SPEED_100 and
    + * SPEED_1000.
    + */
    + val = phy_read_mmd(phydev, DP83867_DEVADDR,
    + DP83867_10M_SGMII_CFG);
    + val &= ~DP83867_10M_SGMII_RATE_ADAPT_MASK;
    + ret = phy_write_mmd(phydev, DP83867_DEVADDR,
    + DP83867_10M_SGMII_CFG, val);
    +
    + if (ret)
    + return ret;
    + }
    +
    /* Enable Interrupt output INT_OE in CFG3 register */
    if (phy_interrupt_is_valid(phydev)) {
    val = phy_read(phydev, DP83867_CFG3);

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