Messages in this thread | | | Subject | Re: [PATCH v2 3/8] dt-bindings: clock: Add YAML schemas for the QCOM GPUCC clock bindings | From | Taniya Das <> | Date | Wed, 27 Nov 2019 04:06:49 +0000 |
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On 11/26/2019 11:41 PM, Stephen Boyd wrote: > Quoting Jeffrey Hugo (2019-11-15 07:11:01) >> On Fri, Nov 15, 2019 at 3:07 AM Taniya Das <tdas@codeaurora.org> wrote: >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml >>> new file mode 100644 >>> index 0000000..c2d6243 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml >>> @@ -0,0 +1,69 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/bindings/clock/qcom,gpucc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Qualcomm Graphics Clock & Reset Controller Binding >>> + >>> +maintainers: >>> + - Taniya Das <tdas@codeaurora.org> >>> + >>> +description: | >>> + Qualcomm grpahics clock control module which supports the clocks, resets and >>> + power domains. >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - qcom,msm8998-gpucc >>> + - qcom,sdm845-gpucc >>> + >>> + clocks: >>> + minItems: 1 >>> + maxItems: 2 >>> + items: >>> + - description: Board XO source >>> + - description: GPLL0 source from GCC >> >> This is not an accurate conversion. GPLL0 was not valid for 845, and >> is required for 8998. > > Thanks for checking Jeff. > > It looks like on 845 there are two gpll0 clocks going to gpucc. From > gpu_cc_parent_map_0: > > "gcc_gpu_gpll0_clk_src", > "gcc_gpu_gpll0_div_clk_src", >
There are branches of GPLL0 which would be connected to most external CCs. It is upto to the external CCs to either use them to source a frequency or not.
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