Re: [PATCH v2 2/2] clk: aspeed: Add RMII RCLK gates for both AST2500 MACs
From
Stephen Boyd <>
Date
Tue, 26 Nov 2019 10:03:19 -0800
Quoting Andrew Jeffery (2019-10-09 19:06:55) > RCLK is a fixed 50MHz clock derived from HPLL that is described by a > single gate for each MAC. > > Signed-off-by: Andrew Jeffery <andrew@aj.id.au> > ---