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    Subject[PATCH 4.19 118/220] clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420
    Date
    From: Joonyoung Shim <jy0922.shim@samsung.com>

    [ Upstream commit d32dd2a1a0f80edad158c9a1ba5f47650d9504a0 ]

    The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on
    exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to
    handle the bit only on exynos5420.

    Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
    [m.szyprow: rewrote commit subject]
    Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
    Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/samsung/clk-exynos5420.c | 3 +--
    1 file changed, 1 insertion(+), 2 deletions(-)

    diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
    index d4f77c4eb277a..ce30862617a6e 100644
    --- a/drivers/clk/samsung/clk-exynos5420.c
    +++ b/drivers/clk/samsung/clk-exynos5420.c
    @@ -634,6 +634,7 @@ static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
    };

    static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
    + GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
    GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
    SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
    };
    @@ -1163,8 +1164,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
    GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
    GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),

    - GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
    -
    /* GEN Block */
    GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
    GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
    --
    2.20.1


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