lkml.org 
[lkml]   [2019]   [Nov]   [21]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
SubjectRe: [PATCH v10 4/6] x86/split_lock: Enumerate split lock detection if the IA32_CORE_CAPABILITIES MSR is not supported
Date

> On Nov 21, 2019, at 4:25 PM, Fenghua Yu <fenghua.yu@intel.com> wrote:
>
> On Thu, Nov 21, 2019 at 02:07:38PM -0800, Andy Lutomirski wrote:
>>
>>
>>>> On Nov 20, 2019, at 5:45 PM, Fenghua Yu <fenghua.yu@intel.com> wrote:
>>>
>>> Architecturally the split lock detection feature is enumerated by
>>> IA32_CORE_CAPABILITIES MSR and future CPU models will indicate presence
>>> of the feature by setting bit 5. But the feature is present in a few
>>> older models where split lock detection is enumerated by the CPU models.
>>>
>>> Use a "x86_cpu_id" table to list the older CPU models with the feature.
>>>
>>
>> This may need to be disabled if the HYPERVISOR bit is set.
>
> How about just keeping this patch set as basic enabling code and
> keep HYPERVISOR out of scope as of now? KVM folks will have better
> handling of split lock in KVM once this patch set is available in
> the kernel.
>
>

You seem to be assuming that certain model CPUs have this feature even if not enumerated. You need to make sure you don’t try to use it in a VM without the hypervisor giving you an indication that it’s available and permitted. My suggestion is to disable model-based enumeration if HYPERVISOR is set. You should also consider probing the MSR to double check even if you don’t think you have a hypervisor.
\
 
 \ /
  Last update: 2019-11-22 03:14    [from the cache]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and my Meterkast|Read the blog