Messages in this thread | | | From | Kevin Hilman <> | Subject | Re: [PATCH] ARM: dts: meson8: fix the size of the PMU registers | Date | Thu, 21 Nov 2019 15:46:09 -0800 |
| |
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> The PMU registers are at least 0x18 bytes wide. Meson8b already uses a > size of 0x18. The structure of the PMU registers on Meson8 and Meson8b > is similar but not identical. > > Meson8 and Meson8b have the following registers in common (starting at > AOBUS + 0xe0): > #define AO_RTI_PWR_A9_CNTL0 0xe0 (0x38 << 2) > #define AO_RTI_PWR_A9_CNTL1 0xe4 (0x39 << 2) > #define AO_RTI_GEN_PWR_SLEEP0 0xe8 (0x3a << 2) > #define AO_RTI_GEN_PWR_ISO0 0x4c (0x3b << 2) > > Meson8b additionally has these three registers: > #define AO_RTI_GEN_PWR_ACK0 0xf0 (0x3c << 2) > #define AO_RTI_PWR_A9_MEM_PD0 0xf4 (0x3d << 2) > #define AO_RTI_PWR_A9_MEM_PD1 0xf8 (0x3e << 2) > > Thus we can assume that the register size of the PMU IP blocks is > identical on both SoCs (and Meson8 just contains some reserved registers > in that area) because the CEC registers start right after the PMU > (AO_RTI_*) registers at AOBUS + 0x100 (0x40 << 2). > > The upcoming power domain driver will need to read and write the > AO_RTI_GEN_PWR_SLEEP0 and AO_RTI_GEN_PWR_ISO0 registers, so the updated > size is needed for that driver to work. > > Fixes: 4a5a27116b447d ("ARM: dts: meson8: add support for booting the secondary CPU cores") > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Queued as a fix for v5.5-rc,
Kevin
| |