Messages in this thread Patch in this message | | | From | Fenghua Yu <> | Subject | [PATCH v10 3/6] x86/split_lock: Enumerate split lock detection by the IA32_CORE_CAPABILITIES MSR | Date | Wed, 20 Nov 2019 16:53:20 -0800 |
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Bits in the IA32_CORE_CAPABILITIES MSR enumerate a few features that are not enumerated through CPUID. Currently bit 5 is defined to enumerate the feature of split lock detection. All other bits are reserved now.
When bit 5 is 1, the feature is supported and feature bit X86_FEATURE_SPLIT_LOCK_DETECT is set. Otherwise, the feature is not available.
The flag shown in /proc/cpuinfo is "split_lock_detect".
Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Reviewed-by: Tony Luck <tony.luck@intel.com> --- arch/x86/include/asm/cpu.h | 5 +++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/common.c | 2 ++ arch/x86/kernel/cpu/intel.c | 19 +++++++++++++++++++ 4 files changed, 27 insertions(+)
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index adc6cc86b062..4e03f53fc079 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -40,4 +40,9 @@ int mwait_usable(const struct cpuinfo_x86 *); unsigned int x86_family(unsigned int sig); unsigned int x86_model(unsigned int sig); unsigned int x86_stepping(unsigned int sig); +#ifdef CONFIG_CPU_SUP_INTEL +void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c); +#else +static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {} +#endif #endif /* _ASM_X86_CPU_H */ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index d708a1f83f40..92be003c02ba 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -220,6 +220,7 @@ #define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF workaround PTE inversion */ #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ +#define X86_FEATURE_SPLIT_LOCK_DETECT ( 7*32+31) /* #AC for split lock */ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index fffe21945374..2ee5fd49266f 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1235,6 +1235,8 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c) cpu_set_bug_bits(c); + cpu_set_core_cap_bits(c); + fpu__init_system(c); #ifdef CONFIG_X86_32 diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 11d5c5950e2d..ce87e2c68767 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -1028,3 +1028,22 @@ static const struct cpu_dev intel_cpu_dev = { }; cpu_dev_register(intel_cpu_dev); + +static void __init split_lock_setup(void) +{ + setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT); +} + +void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) +{ + u64 ia32_core_caps = 0; + + if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES)) + return; + + /* Enumerate features reported in IA32_CORE_CAPABILITIES MSR. */ + rdmsrl(MSR_IA32_CORE_CAPABILITIES, ia32_core_caps); + + if (ia32_core_caps & MSR_IA32_CORE_CAPABILITIES_SPLIT_LOCK_DETECT) + split_lock_setup(); +} -- 2.19.1
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