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    Subject[PATCH AUTOSEL 4.14 036/150] clk: mmp2: fix the clock id for sdh2_clk and sdh3_clk
    Date
    From: Lubomir Rintel <lkundrak@v3.sk>

    [ Upstream commit 4917fb90eec7c26dac1497ada3bd4a325f670fcc ]

    A typo that makes it impossible to get the correct clocks for
    MMP2_CLK_SDH2 and MMP2_CLK_SDH3.

    Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
    Fixes: 1ec770d92a62 ("clk: mmp: add mmp2 DT support for clock driver")
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/mmp/clk-of-mmp2.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/drivers/clk/mmp/clk-of-mmp2.c b/drivers/clk/mmp/clk-of-mmp2.c
    index 0fc75c3959570..d083b860f0833 100644
    --- a/drivers/clk/mmp/clk-of-mmp2.c
    +++ b/drivers/clk/mmp/clk-of-mmp2.c
    @@ -227,8 +227,8 @@ static struct mmp_param_gate_clk apmu_gate_clks[] = {
    /* The gate clocks has mux parent. */
    {MMP2_CLK_SDH0, "sdh0_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH0, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
    {MMP2_CLK_SDH1, "sdh1_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH1, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
    - {MMP2_CLK_SDH1, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
    - {MMP2_CLK_SDH1, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
    + {MMP2_CLK_SDH2, "sdh2_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH2, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
    + {MMP2_CLK_SDH3, "sdh3_clk", "sdh_mix_clk", CLK_SET_RATE_PARENT, APMU_SDH3, 0x1b, 0x1b, 0x0, 0, &sdh_lock},
    {MMP2_CLK_DISP0, "disp0_clk", "disp0_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1b, 0x1b, 0x0, 0, &disp0_lock},
    {MMP2_CLK_DISP0_SPHY, "disp0_sphy_clk", "disp0_sphy_div", CLK_SET_RATE_PARENT, APMU_DISP0, 0x1024, 0x1024, 0x0, 0, &disp0_lock},
    {MMP2_CLK_DISP1, "disp1_clk", "disp1_div", CLK_SET_RATE_PARENT, APMU_DISP1, 0x1b, 0x1b, 0x0, 0, &disp1_lock},
    --
    2.20.1
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