Messages in this thread | | | Subject | Re: [PATCH] perf/x86/intel: Avoid PEBS_ENABLE MSR access in PMI | From | "Liang, Kan" <> | Date | Fri, 15 Nov 2019 09:46:25 -0500 |
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On 11/15/2019 9:07 AM, Peter Zijlstra wrote: > On Fri, Nov 15, 2019 at 05:39:17AM -0800, kan.liang@linux.intel.com wrote: >> From: Kan Liang <kan.liang@linux.intel.com> >> >> The perf PMI handler, intel_pmu_handle_irq(), currently does >> unnecessary MSR accesses when PEBS is enabled. >> >> When entering the handler, global ctrl is explicitly disabled. All >> counters do not count anymore. It doesn't matter if the PEBS is >> enabled or disabled. Furthermore, cpuc->pebs_enabled is not changed >> in PMI. The PEBS status doesn't change. The PEBS_ENABLE MSR doesn't need >> to be changed either. > > PMI can throttle, and iirc x86_pmu_stop() ends up in > intel_pmu_pebs_disable() >
Right, the declaration is inaccurate. I will fix it in v2. But the patch still works for the case of PMI throttle. The intel_pmu_pebs_disable() will update cpuc->pebs_enabled and unconditionally modify MSR_IA32_PEBS_ENABLE. When exiting the handler, current perf re-write the PEBS MSR according to the updated cpuc->pebs_enabled, which is still unnecessary.
Thanks, Kan
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