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SubjectRe: [PATCH v2 1/1] pwm: Convert period and duty cycle to u64
Hi Guru,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on pwm/for-next]
[cannot apply to v5.4-rc7 next-20191114]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url: https://github.com/0day-ci/linux/commits/Guru-Das-Srinagesh/Convert-period-and-duty-cycle-to-u64/20191115-172357
base: https://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git for-next
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=sh

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

In file included from include/linux/printk.h:332:0,
from include/linux/kernel.h:15,
from include/linux/clk.h:13,
from include/linux/mfd/stm32-lptimer.h:12,
from drivers//pwm/pwm-stm32-lp.c:13:
drivers//pwm/pwm-stm32-lp.c: In function 'stm32_pwm_lp_apply':
>> drivers//pwm/pwm-stm32-lp.c:64:27: warning: format '%u' expects argument of type 'unsigned int', but argument 4 has type 'u64 {aka const long long unsigned int}' [-Wformat=]
dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period);
^
include/linux/dynamic_debug.h:125:15: note: in definition of macro '__dynamic_func_call'
func(&id, ##__VA_ARGS__); \
^~~~~~~~~~~
include/linux/dynamic_debug.h:157:2: note: in expansion of macro '_dynamic_func_call'
_dynamic_func_call(fmt,__dynamic_dev_dbg, \
^~~~~~~~~~~~~~~~~~
include/linux/device.h:1751:2: note: in expansion of macro 'dynamic_dev_dbg'
dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~~~~~~~~~~~~~
include/linux/device.h:1751:23: note: in expansion of macro 'dev_fmt'
dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
^~~~~~~
>> drivers//pwm/pwm-stm32-lp.c:64:3: note: in expansion of macro 'dev_dbg'
dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period);
^~~~~~~

vim +64 drivers//pwm/pwm-stm32-lp.c

e70a540b4e0230 Fabrice Gasnier 2017-08-28 @13 #include <linux/mfd/stm32-lptimer.h>
e70a540b4e0230 Fabrice Gasnier 2017-08-28 14 #include <linux/module.h>
e70a540b4e0230 Fabrice Gasnier 2017-08-28 15 #include <linux/of.h>
cce4a833fc6dfd Fabrice Gasnier 2019-04-18 16 #include <linux/pinctrl/consumer.h>
e70a540b4e0230 Fabrice Gasnier 2017-08-28 17 #include <linux/platform_device.h>
e70a540b4e0230 Fabrice Gasnier 2017-08-28 18 #include <linux/pwm.h>
e70a540b4e0230 Fabrice Gasnier 2017-08-28 19
e70a540b4e0230 Fabrice Gasnier 2017-08-28 20 struct stm32_pwm_lp {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 21 struct pwm_chip chip;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 22 struct clk *clk;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 23 struct regmap *regmap;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 24 };
e70a540b4e0230 Fabrice Gasnier 2017-08-28 25
e70a540b4e0230 Fabrice Gasnier 2017-08-28 26 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 27 {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 28 return container_of(chip, struct stm32_pwm_lp, chip);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 29 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 30
e70a540b4e0230 Fabrice Gasnier 2017-08-28 31 /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescaler */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 32 #define STM32_LPTIM_MAX_PRESCALER 128
e70a540b4e0230 Fabrice Gasnier 2017-08-28 33
e70a540b4e0230 Fabrice Gasnier 2017-08-28 34 static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pwm,
71523d1812aca6 Uwe Kleine-König 2019-08-24 35 const struct pwm_state *state)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 36 {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 37 struct stm32_pwm_lp *priv = to_stm32_pwm_lp(chip);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 38 unsigned long long prd, div, dty;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 39 struct pwm_state cstate;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 40 u32 val, mask, cfgr, presc = 0;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 41 bool reenable;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 42 int ret;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 43
e70a540b4e0230 Fabrice Gasnier 2017-08-28 44 pwm_get_state(pwm, &cstate);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 45 reenable = !cstate.enabled;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 46
e70a540b4e0230 Fabrice Gasnier 2017-08-28 47 if (!state->enabled) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 48 if (cstate.enabled) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 49 /* Disable LP timer */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 50 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 51 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 52 return ret;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 53 /* disable clock to PWM counter */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 54 clk_disable(priv->clk);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 55 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 56 return 0;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 57 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 58
e70a540b4e0230 Fabrice Gasnier 2017-08-28 59 /* Calculate the period and prescaler value */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 60 div = (unsigned long long)clk_get_rate(priv->clk) * state->period;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 61 do_div(div, NSEC_PER_SEC);
c91e3234c6035b Fabrice Gasnier 2019-09-18 62 if (!div) {
c91e3234c6035b Fabrice Gasnier 2019-09-18 63 /* Clock is too slow to achieve requested period. */
c91e3234c6035b Fabrice Gasnier 2019-09-18 @64 dev_dbg(priv->chip.dev, "Can't reach %u ns\n", state->period);
c91e3234c6035b Fabrice Gasnier 2019-09-18 65 return -EINVAL;
c91e3234c6035b Fabrice Gasnier 2019-09-18 66 }
c91e3234c6035b Fabrice Gasnier 2019-09-18 67
e70a540b4e0230 Fabrice Gasnier 2017-08-28 68 prd = div;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 69 while (div > STM32_LPTIM_MAX_ARR) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 70 presc++;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 71 if ((1 << presc) > STM32_LPTIM_MAX_PRESCALER) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 72 dev_err(priv->chip.dev, "max prescaler exceeded\n");
e70a540b4e0230 Fabrice Gasnier 2017-08-28 73 return -EINVAL;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 74 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 75 div = prd >> presc;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 76 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 77 prd = div;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 78
e70a540b4e0230 Fabrice Gasnier 2017-08-28 79 /* Calculate the duty cycle */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 80 dty = prd * state->duty_cycle;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 81 do_div(dty, state->period);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 82
e70a540b4e0230 Fabrice Gasnier 2017-08-28 83 if (!cstate.enabled) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 84 /* enable clock to drive PWM counter */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 85 ret = clk_enable(priv->clk);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 86 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 87 return ret;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 88 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 89
e70a540b4e0230 Fabrice Gasnier 2017-08-28 90 ret = regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 91 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 92 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 93
e70a540b4e0230 Fabrice Gasnier 2017-08-28 94 if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) != presc) ||
e70a540b4e0230 Fabrice Gasnier 2017-08-28 95 (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) != state->polarity)) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 96 val = FIELD_PREP(STM32_LPTIM_PRESC, presc);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 97 val |= FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 98 mask = STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 99
e70a540b4e0230 Fabrice Gasnier 2017-08-28 100 /* Must disable LP timer to modify CFGR */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 101 reenable = true;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 102 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 103 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 104 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 105
e70a540b4e0230 Fabrice Gasnier 2017-08-28 106 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask,
e70a540b4e0230 Fabrice Gasnier 2017-08-28 107 val);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 108 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 109 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 110 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 111
e70a540b4e0230 Fabrice Gasnier 2017-08-28 112 if (reenable) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 113 /* Must (re)enable LP timer to modify CMP & ARR */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 114 ret = regmap_write(priv->regmap, STM32_LPTIM_CR,
e70a540b4e0230 Fabrice Gasnier 2017-08-28 115 STM32_LPTIM_ENABLE);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 116 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 117 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 118 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 119
e70a540b4e0230 Fabrice Gasnier 2017-08-28 120 ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, prd - 1);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 121 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 122 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 123
e70a540b4e0230 Fabrice Gasnier 2017-08-28 124 ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty));
e70a540b4e0230 Fabrice Gasnier 2017-08-28 125 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 126 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 127
e70a540b4e0230 Fabrice Gasnier 2017-08-28 128 /* ensure CMP & ARR registers are properly written */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 129 ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
e70a540b4e0230 Fabrice Gasnier 2017-08-28 130 (val & STM32_LPTIM_CMPOK_ARROK),
e70a540b4e0230 Fabrice Gasnier 2017-08-28 131 100, 1000);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 132 if (ret) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 133 dev_err(priv->chip.dev, "ARR/CMP registers write issue\n");
e70a540b4e0230 Fabrice Gasnier 2017-08-28 134 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 135 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 136 ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
e70a540b4e0230 Fabrice Gasnier 2017-08-28 137 STM32_LPTIM_CMPOKCF_ARROKCF);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 138 if (ret)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 139 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 140
e70a540b4e0230 Fabrice Gasnier 2017-08-28 141 if (reenable) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 142 /* Start LP timer in continuous mode */
e70a540b4e0230 Fabrice Gasnier 2017-08-28 143 ret = regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
e70a540b4e0230 Fabrice Gasnier 2017-08-28 144 STM32_LPTIM_CNTSTRT,
e70a540b4e0230 Fabrice Gasnier 2017-08-28 145 STM32_LPTIM_CNTSTRT);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 146 if (ret) {
e70a540b4e0230 Fabrice Gasnier 2017-08-28 147 regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 148 goto err;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 149 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 150 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 151
e70a540b4e0230 Fabrice Gasnier 2017-08-28 152 return 0;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 153 err:
e70a540b4e0230 Fabrice Gasnier 2017-08-28 154 if (!cstate.enabled)
e70a540b4e0230 Fabrice Gasnier 2017-08-28 155 clk_disable(priv->clk);
e70a540b4e0230 Fabrice Gasnier 2017-08-28 156
e70a540b4e0230 Fabrice Gasnier 2017-08-28 157 return ret;
e70a540b4e0230 Fabrice Gasnier 2017-08-28 158 }
e70a540b4e0230 Fabrice Gasnier 2017-08-28 159

:::::: The code at line 64 was first introduced by commit
:::::: c91e3234c6035baf5a79763cb4fcd5d23ce75c2b pwm: stm32-lp: Add check in case requested period cannot be achieved

:::::: TO: Fabrice Gasnier <fabrice.gasnier@st.com>
:::::: CC: Thierry Reding <thierry.reding@gmail.com>

---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
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