Messages in this thread | | | From | Suzuki K Poulose <> | Subject | [PATCH 0/5] arm64: Add workaround for Cortex-A77 erratum 1542418 | Date | Thu, 14 Nov 2019 14:59:13 +0000 |
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This series adds workaround for Arm erratum 1542418 which affects Cortex-A77 cores (r0p0 - r1p0). Affected cores may execute stale instructions from the L0 macro-op cache violating the prefetch-speculation-protection guaranteed by the architecture. This happens when the when the branch predictor bases its predictions on a branch at this address on the stale history due to ASID or VMID reuse.
The workaround is to invalidate the branch history before reusing any ASID for a new address space. This is done by ensuring 60 ASIDs are selected before any ASID is reused.
James Morse (5): arm64: Add MIDR encoding for Arm Cortex-A77 arm64: mm: Workaround Cortex-A77 erratum 1542418 on ASID rollover arm64: Workaround Cortex-A77 erratum 1542418 on boot due to kexec KVM: arm64: Workaround Cortex-A77 erratum 1542418 on VMID rollover KVM: arm/arm64: Don't invoke defacto-CnP on first run
Documentation/arm64/silicon-errata.rst | 2 + arch/arm/include/asm/kvm_mmu.h | 5 ++ arch/arm64/Kconfig | 16 ++++++ arch/arm64/include/asm/cpucaps.h | 3 +- arch/arm64/include/asm/cputype.h | 2 + arch/arm64/include/asm/kvm_mmu.h | 15 ++++++ arch/arm64/include/asm/mmu_context.h | 1 + arch/arm64/kernel/cpu_errata.c | 21 ++++++++ arch/arm64/mm/context.c | 73 +++++++++++++++++++++++++- virt/kvm/arm/arm.c | 23 +++++--- 10 files changed, 151 insertions(+), 10 deletions(-)
-- 2.23.0
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