Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH v2] clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation | Date | Wed, 13 Nov 2019 15:03:01 -0800 |
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Quoting Dmitry Osipenko (2019-10-29 17:48:13) > UART clock is divided using divisor values from DLM/DLL registers when > enable-bit is unset in clk register and clk's divider configuration isn't > taken onto account in this case. This doesn't cause any problems, but > let's add a check for the divider's enable-bit state, for consistency. > > Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > ---
Is this going to be picked up or should I just apply atop the tegra PR?
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