Messages in this thread | | | From | Stephen Boyd <> | Subject | Re: [PATCH 1/5] clk: sprd: add gate for pll clocks | Date | Wed, 13 Nov 2019 14:15:28 -0800 |
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Quoting Chunyan Zhang (2019-10-25 04:13:34) > diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c > index f59d1936b412..d8b480f852f3 100644 > --- a/drivers/clk/sprd/gate.c > +++ b/drivers/clk/sprd/gate.c > @@ -109,3 +120,11 @@ const struct clk_ops sprd_sc_gate_ops = { > }; > EXPORT_SYMBOL_GPL(sprd_sc_gate_ops); > > +#define sprd_pll_sc_gate_unprepare sprd_sc_gate_disable
Why is there a redefine? Just use the function where it is.
> + > +const struct clk_ops sprd_pll_sc_gate_ops = { > + .unprepare = sprd_pll_sc_gate_unprepare, > + .prepare = sprd_pll_sc_gate_prepare, > + .is_enabled = sprd_gate_is_enabled, > +}; > +EXPORT_SYMBOL_GPL(sprd_pll_sc_gate_ops); > diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h > index dc352ea55e1f..598ce607ca0a 100644 > --- a/drivers/clk/sprd/gate.h > +++ b/drivers/clk/sprd/gate.h > @@ -14,16 +14,19 @@ struct sprd_gate { > u32 enable_mask; > u16 flags; > u16 sc_offset; > + u32 udelay;
Does the delay need to be 32 bits wide? Maybe a u8 or u16 will work? Otherwise, make it an unsigned long please because the bit width doesn't matter.
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