Messages in this thread | | | Date | Wed, 13 Nov 2019 15:25:44 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH] drm/sun4i: tcon: Set min division of TCON0_DCLK to 1. |
| |
Hi,
On Wed, Nov 13, 2019 at 01:27:25PM +0000, Tian Yunhao wrote: > The datasheet of V3s (and various other chips) wrote > that TCON0_DCLK_DIV can be >= 1 if only dclk is used, > and must >= 6 if dclk1 or dclk2 is used. As currently > neither dclk1 nor dclk2 is used (no writes to these > bits), let's set minimal division to 1. > > If this minimal division is 6, some common dot clock > frequencies can't be produced (e.g. 30MHz will not be > possible and will fallback to 25MHz), which is > obviously not an expected behaviour. > > Signed-off-by: Yunhao Tian <t123yh@outlook.com>
Applied, thanks.
I had to update your author name to match the one in the Signed-off-by. You probably want to check your git configuration to remain consistent.
Maxime [unhandled content-type:application/pgp-signature] | |