Messages in this thread | | | Subject | Re: [PATCH v6 2/3] dwc: PCI: intel: PCIe RC controller driver | From | Dilip Kota <> | Date | Thu, 14 Nov 2019 11:51:58 +0800 |
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On 11/13/2019 5:59 PM, Gustavo Pimentel wrote: > On Wed, Nov 13, 2019 at 7:21:21, Dilip Kota <eswara.kota@linux.intel.com> > wrote: > [...] > +static struct platform_driver intel_pcie_driver = { > + .probe = intel_pcie_probe, > + .remove = intel_pcie_remove, > + .driver = { > + .name = "intel-gw-pcie", > + .of_match_table = of_intel_pcie_match, > + .pm = &intel_pcie_pm_ops, > + }, > +}; > +builtin_platform_driver(intel_pcie_driver); > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 29d6e93fd15e..548e22e07a52 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -673,6 +673,7 @@ > #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ > #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ > #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ > +#define PCI_EXP_LNKCTL2_HASD 0x0020 /* HW Autonomous Speed Disable */ > #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ > #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ > #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ > -- > 2.11.0 > > Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Thanks for reviewing the patch.
Regards, Dilip > >
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