Messages in this thread | | | Subject | Re: [PATCH 3/4] gpio: sifive: Add GPIO driver for SiFive SoCs | Date | Tue, 12 Nov 2019 14:07:21 +0109 | From | Marc Zyngier <> |
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On 2019-11-12 13:21, Yash Shah wrote: > Adds the GPIO driver for SiFive RISC-V SoCs. > > Signed-off-by: Wesley W. Terpstra <wesley@sifive.com> > [Atish: Various fixes and code cleanup] > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Signed-off-by: Yash Shah <yash.shah@sifive.com>
[...]
> +static int sifive_gpio_child_to_parent_hwirq(struct gpio_chip *gc, > + unsigned int child, > + unsigned int child_type, > + unsigned int *parent, > + unsigned int *parent_type) > +{ > + /* All these interrupts are level high in the CPU */ > + *parent_type = IRQ_TYPE_LEVEL_HIGH;
It is bizare that you enforce LEVEL_HIGH here, while setting it to NONE in the PLIC driver. These things should be consistent.
> + *parent = child + 7;
Irk, magic numbers...
M. -- Jazz is not dead. It just smells funny...
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