lkml.org 
[lkml]   [2019]   [Nov]   [11]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.3 094/193] dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer
    Date
    From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>

    [ Upstream commit 68fe2b520cee829ed518b4b1f64d2a557bcbffe1 ]

    In AXI DMA simple mode also pass MSB bits of source and destination
    address to xilinx_write function. It fixes simple AXI DMA operation
    mode using 64-bit addressing.

    Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
    Link: https://lore.kernel.org/r/1569495060-18117-2-git-send-email-radhey.shyam.pandey@xilinx.com
    Signed-off-by: Vinod Koul <vkoul@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/dma/xilinx/xilinx_dma.c | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
    index e7dc3c4dc8e07..1fbe0258578b0 100644
    --- a/drivers/dma/xilinx/xilinx_dma.c
    +++ b/drivers/dma/xilinx/xilinx_dma.c
    @@ -1354,7 +1354,8 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
    node);
    hw = &segment->hw;

    - xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR, hw->buf_addr);
    + xilinx_write(chan, XILINX_DMA_REG_SRCDSTADDR,
    + xilinx_prep_dma_addr_t(hw->buf_addr));

    /* Start the transfer */
    dma_ctrl_write(chan, XILINX_DMA_REG_BTT,
    --
    2.20.1


    \
     
     \ /
      Last update: 2019-11-11 19:53    [W:4.070 / U:0.212 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site