Messages in this thread | | | Date | Fri, 1 Nov 2019 17:01:34 +0100 | From | Ondřej Jirman <> | Subject | Re: [PATCH] cpufreq: sun50i: Fix CPU speed bin detection |
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On Fri, Nov 01, 2019 at 04:07:01PM +0100, Maxime Ripard wrote: > On Thu, Oct 31, 2019 at 07:13:58PM +0100, Ondrej Jirman wrote: > > I have failures to boot on Orange Pi 3, because this driver determined > > that my SoC is from the normal bin, but my SoC only works reliably with > > the OPP values for the slowest bin. > > > > Looking at BSP code, I found that efuse values have following meanings > > on H6: > > > > - 0b000 invalid (interpreted in vendor's BSP as normal bin) > > - 0b001 slowest bin > > - 0b011 normal bin > > - 0b111 fastest bin > > > > Let's play it safe and interpret 0 as the slowest bin, but fix detection > > of other bins to match vendor code. > > > > Fixes: f328584f7bff ("cpufreq: Add sun50i nvmem based CPU scaling driver") > > Signed-off-by: Ondrej Jirman <megous@megous.com> > > Acked-by: Maxime Ripard <mripard@kernel.org> > > Out of curiosity, which OPP table is being used? I guess it's one of > the dozens of patches sitting there...
I'm using one from Orange Pi 3's fex file from Xunlong:
https://github.com/orangepi-xunlong/OrangePiH6_external/blob/master/sys_config/OrangePiH6_3_sys_config.fex https://megous.com/git/linux/commit/?h=ths-5.4&id=7b409e83b4ac70f3435886da6a26cecf9af77213
This one doesn't really differentiate between normal/fast bins.
There's also another one in the Allwinner DTS files:
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L349
which seems to be the one used by Yangtao Li in the dt-bindings docummentation.
regards, o.
> Maxime
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