Messages in this thread Patch in this message | | | From | Peng Fan <> | Subject | [PATCH] clk: imx: clk-composite-8m: add lock to gate/mux | Date | Fri, 1 Nov 2019 10:16:19 +0000 |
| |
From: Peng Fan <peng.fan@nxp.com>
There is a lock to diviver in the composite driver, but that's not enought. lock to gate/mux are also needed to provide exclusive access to the register.
Fixes: d3ff9728134e ("clk: imx: Add imx composite clock") Signed-off-by: Peng Fan <peng.fan@nxp.com> --- drivers/clk/imx/clk-composite-8m.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index e0f25983e80f..20f7c91c03d2 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -142,6 +142,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, mux->reg = reg; mux->shift = PCG_PCS_SHIFT; mux->mask = PCG_PCS_MASK; + mux->lock = &imx_ccm_lock; div = kzalloc(sizeof(*div), GFP_KERNEL); if (!div) @@ -161,6 +162,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, gate_hw = &gate->hw; gate->reg = reg; gate->bit_idx = PCG_CGC_SHIFT; + gate->lock = &imx_ccm_lock; hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ops, div_hw, -- 2.16.4
| |