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    Subject[PATCH 5.3 073/166] clk: imx: clk-pll14xx: unbypass PLL by default
    Date
    From: Peng Fan <peng.fan@nxp.com>

    [ Upstream commit a9aa8306074d9519dd6e5fdf07240b01bac72e04 ]

    When registering the PLL, unbypass the PLL.
    The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
    we will expose EXT_BYPASS to clk driver for mux usage, and keep
    BYPASS inside pll14xx usage. The PLL has a restriction that
    when M/P change, need to RESET/BYPASS pll to avoid glitch, so
    we could not expose BYPASS.

    To make it easy for clk driver usage, unbypass PLL which does
    not hurt current function.

    Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
    Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com
    Signed-off-by: Stephen Boyd <sboyd@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/imx/clk-pll14xx.c | 5 +++++
    1 file changed, 5 insertions(+)

    diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c
    index 656f48b002dd3..7a815ec76aa5c 100644
    --- a/drivers/clk/imx/clk-pll14xx.c
    +++ b/drivers/clk/imx/clk-pll14xx.c
    @@ -368,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
    struct clk_pll14xx *pll;
    struct clk *clk;
    struct clk_init_data init;
    + u32 val;

    pll = kzalloc(sizeof(*pll), GFP_KERNEL);
    if (!pll)
    @@ -399,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name,
    pll->rate_table = pll_clk->rate_table;
    pll->rate_count = pll_clk->rate_count;

    + val = readl_relaxed(pll->base + GNRL_CTL);
    + val &= ~BYPASS_MASK;
    + writel_relaxed(val, pll->base + GNRL_CTL);
    +
    clk = clk_register(NULL, &pll->hw);
    if (IS_ERR(clk)) {
    pr_err("%s: failed to register pll %s %lu\n",
    --
    2.20.1


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