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    Subject[PATCH 5.2 197/313] e1000e: add workaround for possible stalled packet
    Date
    From: Kai-Heng Feng <kai.heng.feng@canonical.com>

    [ Upstream commit e5e9a2ecfe780975820e157b922edee715710b66 ]

    This works around a possible stalled packet issue, which may occur due to
    clock recovery from the PCH being too slow, when the LAN is transitioning
    from K1 at 1G link speed.

    Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204057

    Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
    Tested-by: Aaron Brown <aaron.f.brown@intel.com>
    Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/net/ethernet/intel/e1000e/ich8lan.c | 10 ++++++++++
    drivers/net/ethernet/intel/e1000e/ich8lan.h | 2 +-
    2 files changed, 11 insertions(+), 1 deletion(-)

    diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c b/drivers/net/ethernet/intel/e1000e/ich8lan.c
    index cdae0efde8e64..7998a73b6a0fa 100644
    --- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
    +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
    @@ -1429,6 +1429,16 @@ static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
    else
    phy_reg |= 0xFA;
    e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
    +
    + if (speed == SPEED_1000) {
    + hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
    + &phy_reg);
    +
    + phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
    +
    + hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
    + phy_reg);
    + }
    }
    hw->phy.ops.release(hw);

    diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h
    index eb09c755fa172..1502895eb45dd 100644
    --- a/drivers/net/ethernet/intel/e1000e/ich8lan.h
    +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h
    @@ -210,7 +210,7 @@

    /* PHY Power Management Control */
    #define HV_PM_CTRL PHY_REG(770, 17)
    -#define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100
    +#define HV_PM_CTRL_K1_CLK_REQ 0x200
    #define HV_PM_CTRL_K1_ENABLE 0x4000

    #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28)
    --
    2.20.1


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